STMicroelectronics M74HC107 Dual J-K Flip-Flop Datasheet

The document describes the features and characteristics of the M74HC107 model, including high speed, low power consumption, high noise immunity, and symmetrical output impedance.


STMicroelectronics M74HC107 Dual J-K Flip-Flop Datasheet - cover page
Brand
STMicroelectronics
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
11
File format
PDF
File size
165 KB
Published
10 August, 2012
Updated
28 September, 2023
MD5 checksum
10D52D72D6DA82CE6483E30952278416

About this manual

The M74HC107 is a high-speed CMOS dual J-K flip-flop fabricated with silicon gate 2C MOS technology. The device features independent J, K, CLOCK, and CLEAR inputs for each flip-flop, along with Q and Q outputs. The CLEAR function operates independently of the clock and is activated by a logic low level on the input.

What's inside

  • Description
  • Pin Connection
  • Absolute Maximum Ratings
  • DC Specifications
  • AC Electrical Characteristics
  • Test Circuit
  • Mechanical Data

Specifications

Maximum Clock Frequency80 MHz (Typ.) at VCC = 6V
Low Power Dissipation2µA (Max.) at TA=25°C
Operating Voltage Range2V to 6V
High Noise Immunity28 % VCC (Min.)
Output Impedance4mA (Min)
Supply Voltage-0.5 to +7 V
Operating Temperature-55 to 125 °C

Frequently asked questions

How does the CLEAR function operate?

The CLEAR function is independent of the clock and is accomplished by a logic low on the input.

What is the technology used for the M74HC107?

It is fabricated with silicon gate 2C MOS technology.

Are the flip-flops edge sensitive?

Yes, they are edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

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