The STLVD111 is a programmable low voltage 1:10 differential LVDS clock driver with 100ps part-to-part skew and 50ps bank skew. It features a differential design that meets LVDS specifications for driver outputs and receiver inputs. The driver has a reference voltage available output VBB, a low voltage VCC range of 2.375V to 2.625V, high signalling rate capability (exceeds 622MHz), support for open, short and terminated input fail-safe (low output state), and programmable drivers power off control.
The STLVD111 is a low-skew programmable 1-to-10 differential LVDS driver specifically designed for clock distribution applications. It features a 11-bit shift register with serial input and a control register to enable or power off each output channel and select the clock input. The device supports high signaling rates exceeding 622MHz and is optimized for low gate-to-gate skew within the device.
| Part-to-part skew | 100 ps |
|---|---|
| Bank skew | 50 ps |
| Operating free-air temperature range | -40 to 85 °C |
| Supply voltage (VCC) | 2.375 V to 2.625 V |
| Maximum input frequency (fMAX) | 900 MHz |
| Package type | TQFP32 |
In Standard Mode, the device is not programmable; all clock outputs are enabled and the input is selected via the SI pin.
The device supports high signalling rates that exceed 622MHz.