This document is about STP1031LGA suppliers' information, including supplier names and contact information
This document is a technical datasheet for the Sun Microsystems STP1031, also known as the UltraSPARC-II. It describes a high-performance, highly-integrated superscalar processor implementing the SPARC-V9 64-bit RISC architecture with Visual Instruction Set (VIS) capabilities.
The processor supports up to four instructions per cycle and includes features such as an integrated second-level cache controller, multi-processor support, and compatibility with existing UltraSPARC-I based systems. It operates at voltages of 3.3V and 2.6V within a 787-pin Ceramic Land Grid Array (LGA) package.
| Architecture | SPARC-V9 64-bit RISC |
|---|---|
| Clock Frequency Support | 3.3V and 2.6 V |
| Package Type | 787-Pin Ceramic Land Grid Array (LGA) |
| Process Technology | 0.35um 5-Layer Metal CMOS Process |
| Instruction Cache Size | 16-Kilobyte |
| Data Cache Size | 16-Kilobyte |
The STP1031 implements the SPARC-V9 64-bit RISC architecture.
Yes, it provides software compatibility with existing UltraSPARC-I based systems.