This application note describes how to configure the STR7 interrupt controller (EIC) to be able to handle IRQ and FIQ exceptions, and therefore how it can be customized for your own application requirements
This document provides a description of using the Enhanced Interrupt Controller (EIC) on STR7 microcontrollers to handle IRQ and FIQ exceptions. It details how to configure the controller to meet specific application requirements.
The guide covers fundamental concepts such as exception entry and exit mechanisms, priority levels for various interrupts, and vector table configuration. It also includes examples of interrupt handling in C code and explains the differences between using standard assembly versus compiler-specific keywords like __irq.
| Target Microcontroller Family | STR7 |
|---|---|
| Development Environment Version | RVDK 2.1 |
The highest priority is Reset, followed by Data Abort, FIQ (Fast), IRQ (Normal), Prefetch Abort, SWI, and finally Undefined instruction.
Yes, but any exception handler code written with the Thumb instruction set will return the processor to ARM state because the program counter must go back to the original application code which uses ARM instructions.
The Enhanced Interrupt Controller handles multiple interrupt channels, priority levels, and automatic vectorization when a peripheral generates an IRQ line.