STMicroelectronics AN1776 Interrupt Handling for STR7 Microcontrollers

This application note describes how to configure the STR7 interrupt controller (EIC) to be able to handle IRQ and FIQ exceptions, and therefore how it can be customized for your own application requirements


STMicroelectronics AN1776 Interrupt Handling for STR7 Microcontrollers - cover page
Brand
STMicroelectronics
Category
microcontrollers
Document type
Application Note
Language
English
Pages
13
File format
PDF
File size
78 KB
Published
07 August, 2012
Updated
30 September, 2023
Model
STR7
MD5 checksum
5735DA07F3F5BB47F77B3E4D2FD5B9B0

About this manual

This document provides a description of using the Enhanced Interrupt Controller (EIC) on STR7 microcontrollers to handle IRQ and FIQ exceptions. It details how to configure the controller to meet specific application requirements.

The guide covers fundamental concepts such as exception entry and exit mechanisms, priority levels for various interrupts, and vector table configuration. It also includes examples of interrupt handling in C code and explains the differences between using standard assembly versus compiler-specific keywords like __irq.

What's inside

  • Exception Entry and Exit
  • Exception Priorities
  • Exception Vectors
  • ARM or Thumb State
  • IRQ vs FIQ Interrupts
  • Simple Interrupt Handling in C
  • Interrupt Handling Using the EIC
  • EIC Overview

Specifications

Target Microcontroller FamilySTR7
Development Environment VersionRVDK 2.1

Frequently asked questions

What is the priority order of exceptions in STR7 microcontrollers?

The highest priority is Reset, followed by Data Abort, FIQ (Fast), IRQ (Normal), Prefetch Abort, SWI, and finally Undefined instruction.

Can exception handlers be written in Thumb instructions?

Yes, but any exception handler code written with the Thumb instruction set will return the processor to ARM state because the program counter must go back to the original application code which uses ARM instructions.

How does the EIC manage peripheral interrupts?

The Enhanced Interrupt Controller handles multiple interrupt channels, priority levels, and automatic vectorization when a peripheral generates an IRQ line.

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