Altera EP20K100E FPGA I/O Pins Datasheet

EP20K100E I/O Pins

Altera EP20K100E FPGA I/O Pins Datasheet - cover page
Brand
EP20K100E
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
10
File format
PDF
File size
124 KB
Published
13 July, 2012
Updated
30 September, 2023
MD5 checksum
94F816BA06AC05FE6E6679D828AC92F5
PDF
Altera EP20K100E FPGA I/O Pins Datasheet PDF

About this manual

This document details the pinout configuration for the Altera EP20K100E Field-Programmable Gate Array (FPGA). It lists the function of each pin across various package types, including TQFP, PQFP, and BGA variants.

The table organizes pins by bank number and function, covering general I/O pins, power supply connections (VCCINT, VCCIO, GND), and specific control signals such as configuration pins (CONF_DONE, nSTATUS) and clock inputs.

What's inside

  • I/O Pin Assignments
  • Package Types
  • Power Supply Pins
  • Configuration Signals
  • Clock Pins
  • Bank Definitions

Specifications

Device ModelEP20K100E
Supported Packages144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin FineLine BGA, 356-Pin FineLine BGA

Frequently asked questions

What are the available package types for the EP20K100E?

The device is available in 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin FineLine BGA, and 356-Pin FineLine BGA packages.

What is the function of the CONF_DONE pin?

The CONF_DONE pin is used for configuration status indication.

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