S-MOS SSC5000 Series Standard Cell Datasheet


S-MOS SSC5000 Series Standard Cell Datasheet - cover page
Brand
SSC5000
Category
INTEGRATED CIRCUITS
Document type
Datasheet
Language
English
Pages
3
File format
PDF
File size
186 KB
Published
12 June, 2012
Updated
12 June, 2012
MD5 checksum
D4CC4AD8EBB98216FEC0ED9B5B4ED3C1

About this manual

The S-MOS SSC5000 series is a family of high-performance standard cell circuits manufactured on a 0.8 micron double-metal N-well CMOS process. The series features gate delays of 300 picoseconds and offers various output driver types, including single outputs up to 24mA and parallel outputs up to 48mA. It is designed for high pin count applications with a low gate-to-pads ratio and supports optional tight pitch I/O for TAB assembly technology.

What's inside

  • Description
  • Features
  • Product Configuration
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • Package List

Specifications

Process Technology0.8 micron (drawn) channel length N-well double metal CMOS
Typical Gate Delay300 picoseconds
Single Output Driver Current24mA
Parallel Output Driver Current48mA
RAM Block Size128x8 bits to 8Kx32 bits
Power Supply Voltage (Typical)5.0V

Frequently asked questions

What is the typical gate delay for the SSC5000 series?

The typical gate delay is 300 picoseconds for NAND gates with FO=2 and 2mm AL.

What are the available RAM block sizes?

High-speed and silicon-efficient RAM blocks are available in sizes ranging from 128x8 bits to 8Kx32 bits.

What is the maximum power supply voltage?

The absolute maximum rating for the power supply voltage is 7.0V.

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