The HY5DU121622CTP is a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
This document is a general product description for the Hynix HY5DU121622CTP, a 512Mb CMOS Double Data Rate (DDR) Synchronous DRAM. It is ideally suited for main memory applications requiring large memory density and high bandwidth. The device features fully synchronous operations referenced to both rising and falling edges of the clock, with data paths internally pipelined and 2-bit prefetched to achieve very high bandwidth.
| Capacity | 512Mb (32Mx16) |
|---|---|
| Organization | 8M x 16 x 4 banks |
| Power Supply | 2.5V +/- 0.1V |
| Interface | SSTL_2 |
| Package | 66pin TSOP-II |
| Max Data Rate | 500Mbps/pin |
The maximum data rate is 500Mbps per pin.
The device supports 8192 refresh cycles every 64ms.
The pin pitch is 0.65mm.