Update: 30 September, 2023
AL5DAxxxx 3.3V, 5V Asynchronous Dual-Port SRAM is a dual-port SRAM produced by AverLogic Technologies, Corp. that supports 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit, has fully asynchronous dual-port SRAM, aimed at the communications market, with a maximum access time of 30ns, supports 16/18-bit devices for byte write/read, supports 3 modes of on-chip arbitration logic: Busy, Interrupt and Semaphore, Busy scheme circuit arbitrates between 2 ports, interrupt mechanism allows port to port communication, full hardware support of semaphore to permit software handshaking between ports, supports multiple pin selection for Master or Slave mode: VIH M/S = for BUSY output flag on master; VIL M/S = for BUSY input flag on slave, can expand the data bus to 32/36 bits or more using master/slave chip select when using more than one device, supports 3.3v and 5v series low power, is compatible and functionally equivalent to IDT or Cypress, and is available in 52-PLCC, 68-PLCC, 84-PLCC, 64-TQFP/STQFP, 80-TQFP, 100-TQFP.
File format: PDF
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MD5 Checksum: B8A7E4BDB38D6E4437A6431D30A5DFCD
Publication date: 05 June, 2012
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PDF Link: AVERLOGIC AL5DAxxxx 3.3V 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit PDF