Anachip PA7540 PEEL Array Programmable Electrically Erasable Logic Array Datasheet

PA7540 is a Programmable Electrically Erasable Logic (PEEL™) Array product, which offers high integration, various logic functions and registers, and high-speed performance. It is suitable for combinatorial, synchronous, and asynchronous logic applications.


Anachip PA7540 PEEL Array Programmable Electrically Erasable Logic Array Datasheet - cover page
Brand
CANACHIP
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
10
File format
PDF
File size
236 KB
Published
04 June, 2012
Updated
28 September, 2023
MD5 checksum
0ED5B5C50F629D0C731829112B433330

About this manual

The PA7540 is a member of the PEEL™ Array family based on ICT’s CMOS EEPROM technology. It provides 20 I/O pins, 2 global clocks, 40 registers/latches, and 84 product terms, delivering high‑speed operation (up to 71.4 MHz) for combinatorial, synchronous and asynchronous logic applications.

Development is supported by Anachip’s WinPLACE software and popular third‑party programmers. The device is available in DIP‑24, SOIC‑24 and PLCC‑28 packages, with both commercial (0 °C to 70 °C) and industrial (‑40 °C to +85 °C) temperature grades.

What's inside

  • General Description
  • Inside the Logic Array
  • Logic Control Cell (LCC)
  • Multiple Outputs Per Logic Cell
  • Global Cells
  • PEEL™ Array Development Support
  • Programming
  • Design Security and Signature Word
  • Absolute Maximum Ratings
  • Operating Ranges

Specifications

Supply Voltage (Commercial)4.75 V – 5.25 V
Number of I/O Pins20
Number of Registers/Latches40
Product Terms84
Internal Propagation Delay10 ns
External Propagation Delay15 ns

Frequently asked questions

How many I/O pins does the PA7540 provide?

The device has 20 I/O pins.

Which software is used to develop designs for the PA7540?

Anachip’s WinPLACE Development Software supports PA7540 development.

Download PDF (236 KB)