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The PDSP16112 series is a 16×12‑bit complex multiplier IC featuring four pipeline multiplier sections, a 17‑bit adder and subtractor, and support for two's‑complement arithmetic. It operates at up to 20 MHz (PDSP16112A) and provides separate real and imaginary outputs.
The document includes pin‑out tables, functional description, typical applications such as FFT butterfly processors, electrical and AC characteristics, and ordering information for various package types (PGA, QFP, etc.).
| Output high voltage (Voh) | 2.4 V typ. |
|---|---|
| Output low voltage (Vol) | 0.6 V typ. |
| Input high voltage (Vih) | 2.8 V |
| Input low voltage (Vil) | 0.8 V |
| Maximum clock frequency | 20 MHz typ. (PDSP16112A) |
| Package power dissipation | 500 mW max. |
The PDSP16112A can operate up to 20 MHz typical clock frequency.
The series is available in PGA, QFP, and other high‑reliability packages such as BO AC and BO GG.
The device can dissipate up to 500 mW.