The 54/7492A (also listed as 54LS/74LS92) is a 4‑bit ripple type divide‑by‑twelve counter. It contains four master/slave flip‑flops that provide a divide‑by‑two section and a divide‑by‑six section, each with its own clock input triggered on the HIGH‑to‑LOW transition. The device can operate in multiple counting modes, including a pure divide‑by‑twelve mode or separate divide‑by‑two and divide‑by‑six functions.
The datasheet provides detailed pinout information, connection diagrams, and electrical characteristics such as input high currents, power‑supply current, maximum count frequencies, propagation delays, and pulse‑width specifications. These parameters are essential for designers integrating the counter into digital logic circuits.
| Input HIGH Current (CP0) | 1.0 mA |
|---|---|
| Power Supply Current | 39 mA – 45 mA |
| Maximum Count Frequency (CP0 input) | 32 MHz |
| Pulse Width HIGH (CP1) | 30 ns |
It is a 4‑bit ripple type divide‑by‑twelve counter.
The device consists of four master/slave flip‑flops.
Each section has a separate clock input that initiates state changes on the HIGH‑to‑LOW transition.
The maximum count frequency for the CP0 input is 32 MHz.