LXT901 Universal Ethernet Interface Adapter Datasheet


LXT901 Universal Ethernet Interface Adapter Datasheet - cover page
Brand
LXT901
Document type
Datasheet
Language
English
Pages
29
File format
PDF
File size
1.6 MB
Published
08 May, 2012
Updated
08 May, 2012
MD5 checksum
A8BFEC06C978C007D630ECAB82E8965B

About this manual

The LXT901 is a universal Ethernet interface adapter designed for IEEE 802.3 physical‑layer applications. It provides all active circuitry needed to connect standard 802.3 controllers to either 10BASE‑T twisted‑pair or AUI drop cables, supporting 10 Mbps Ethernet and full‑duplex 20 Mbps operation. Integrated Manchester encoder/decoder, automatic polarity correction, and selectable termination impedance simplify board design and ensure FCC‑compliant EMI performance.

The device includes four LED drivers for status indication, programmable impedance drivers, and multiple loopback and test modes. It is available in 64‑pin TQFP and 44‑pin PLCC packages and operates from a single 5 V supply. Detailed pin descriptions, controller‑compatibility modes, and timing diagrams are provided for designers.

What's inside

  • Functional Features
  • Convenience Features
  • Diagnostic Features
  • Pin Assignments
  • Pin Descriptions
  • Functional Description
  • Controller Compatibility Modes
  • Transmit Function
  • Jabber Control Function
  • Loopback Function

Specifications

Supported Ethernet Speeds10 Mbps (half‑duplex) and 20 Mbps full‑duplex
Package Options64‑pin TQFP and 44‑pin PLCC
Integrated FiltersSimplify FCC‑compliant EMI performance
LED DriversFour open‑drain drivers (receive, transmit, link, collision)
Clock Output10 MHz transmit clock (TCLK)
Crystal Requirement20 MHz crystal (or external 20 MHz clock)

Frequently asked questions

How does the LXT901 handle reversed polarity on the twisted‑pair input?

It automatically detects reversed polarity and corrects it, indicating the condition on the PLR pin.

What package types are available for the LXT901?

The device is offered in 64‑pin TQFP and 44‑pin PLCC packages.

How is link integrity testing enabled?

Link integrity testing is enabled by tying pin 8 (LD) high; the chip then transmits test pulses and enters a link‑fail state if no pulses are detected within 50‑150 ms.

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