This is a product description file that introduces the features and characteristics of the FPSLIC™ product.
The AT94S Secure Series combines an AT40K SRAM‑based FPGA with an AVR® 8‑bit RISC microcontroller and a secure configuration EEPROM. It offers 5 000 to 40 000 FPGA gates, up to 36 KB of SRAM, and a range of peripherals such as UARTs, timers, and a two‑wire serial interface.
The manual details the in‑system programming (ISP) flow, the serial configurator bus protocol, and the bit‑ordering rules required to read and write the EEPROM. It also provides programming summaries, timing characteristics, and reference schematics for developers integrating the device into handheld or portable applications.
| Configuration Memory Size | 1 Mbit |
|---|---|
| FPGA Gates (AT94S40AL) | 40K |
| Operating Voltage | 3.0 – 3.6 V |
| AVR Programmable I/O Lines | 8 / 16 / 16 |
| Global FPGA Clocks | 8 |
| Typical AVR Performance @ 25 MHz | 19 MIPS |
Each AT94S device includes a 1 Mbit configuration EEPROM.
The AT94S40AL version provides 40 K usable FPGA gates.
The devices operate from 3.0 V to 3.6 V.
The AT94S includes eight global FPGA clocks.