This document describes the clock synchronization issue of the PCI2050B chip in a specific mode and provides a workaround.
The document describes an errata for the PCI2050 bridge device where the Trst‑CLK timing is out of specification. In the 66 MHz primary, 33 MHz secondary mode the dividing DFF stays in reset after primary reset, causing SCLK outputs to remain low.
Workarounds include writing bit 6 of the Bridge Control Register to trigger a secondary bus reset and adding a delay circuit to meet the required 100 µs timing. The notice also contains TI's legal disclaimer and warranty information.
| Primary clock frequency (66/33 mode) | 66 MHz |
|---|---|
| Secondary clock frequency (66/33 mode) | 33 MHz |
| Required S_CLK activation time before S_RST de‑assertion | 100 µs |
The Trst‑CLK timing is out of specification; SCLK stays low after primary reset when operating in 66 MHz primary, 33 MHz secondary mode.
Both PCI2050A and PCI2050B are affected.