DL5000 is the industry's first Fast Field Programmable Gate Array (FFPGA™) family. Utilizing a breakthrough in field programmable interconnect techniques called Active Repeaters, this family provides unprecedented system level performance. High operating frequencies combined with fast ECL, GTL and PECL input and output structures make these devices ideal for high-speed interfaces, subsystems and core logic.
The DL5000 family introduces DynaChip’s patented Active Repeater architecture, delivering high‑speed ECL, PECL and GTL I/O levels and predictable routing delays. Devices range from 1,000 to 10,000 gates and feature six low‑skew clock trees, making them suitable for high‑performance telecommunications, test equipment, and server interfaces.
SRAM‑based programming allows in‑circuit configuration and unlimited re‑programming, while the architecture provides deterministic performance regardless of fan‑out. Detailed specifications, performance tables, and package information are provided for the DL5064, DL5256, and DL5528 devices.
| Data and Clock Rates | up to 270 MHz |
|---|---|
| Complex Operations Frequency | up to 200 MHz |
| Input Block Register Setup Time | 800 ps |
| Output Block Register Clock‑to‑out | 1.6 ns |
| Interface Levels | ECL, PECL and GTL |
| Gate Count Range | 1,000 to 10,000 gates |
| Clock Trees | 6 low‑skew |
The DL5000 family supports data and clock rates up to 270 MHz.
Complex operations can run up to 200 MHz.
The device supports ECL, PECL, and GTL interface levels.