LM3S601 microcontroller selection guide, introduces the features and characteristics of the microcontroller, including 32-bit RISC performance, internal storage, general timer, watchdog timer, etc.
This guide introduces the LM3S601 microcontroller, a 32‑bit ARM Cortex‑M3 device optimized for low‑cost embedded applications. It highlights key features such as a 50 MHz core, hardware division, single‑cycle multiply, nested vector interrupt controller, and various power‑saving options.
The document provides detailed technical information including a high‑level block diagram, pin‑out diagrams, signal tables, package options, and a list of typical target applications such as factory automation, building automation, and motor control. Appendices contain company contact information for ZLG. This manual is written in Chinese.
| Core Architecture | ARM Cortex‑M3 v7M |
|---|---|
| Maximum Operating Frequency | 50 MHz |
| Flash Memory | 32 KB single‑cycle Flash |
| SRAM | 8 KB single‑cycle SRAM |
| GPIO Pins | Up to 36 configurable GPIO pins |
| Interrupts | 26 interrupts with 8 priority levels |
| Timers | 3 general‑purpose timers (configurable as 32‑bit or two 16‑bit) |
| LDO Output Voltage | Programmable 2.25 V–2.75 V |
The LM3S601 operates up to 50 MHz.
It includes 32 KB of single‑cycle Flash memory.
The device offers up to 36 configurable GPIO pins.