AN-AX1000-007-V10-CH-DAC Manual

This document introduces the use of AX1003's built-in 10Bit R2R DAC, including trigger mode, output buffer, etc., and gives detailed configuration steps.


AN-AX1000-007-V10-CH-DAC Manual - cover page
Brand
AN-AX1000-007-V10-CH-DAC
Category
Other Electronics
Document type
User Manual
Language
Chinese
Pages
6
File format
PDF
File size
161 KB
Published
04 January, 2012
Updated
30 September, 2023
MD5 checksum
17AAC80CD91A90292923DF0FA6D3B233

About this manual

The AX1003 integrates a 10‑bit R‑to‑R DAC whose reference voltage is AVDD. The output voltage follows the formula DAC_OUT = AVDD × (DIN / 1024). The DAC shares address space with the ADC registers DACH (41H) and DACL (42H), and can be configured for different trigger modes.

Two trigger modes are supported: a write‑trigger mode where data is output immediately after DACH is written, and a timer‑trigger mode where output occurs on Timer1 or Timer2 interrupts. The DAC output buffer can be enabled or disabled via the DACBE bit, allowing easy matching to external amplification circuits. The manual also includes a full register map and sample assembly code for generating a 1 kHz sine wave using Timer2. This manual is written in Chinese.

What's inside

  • Introduction
  • DAC Architecture
  • Trigger Modes
  • Write Trigger Mode
  • Timer Trigger Mode
  • Output Buffer
  • DAC Configuration Steps
  • Register Map
  • Example Code

Specifications

Resolution10 bit
ArchitectureR‑to‑R resistor network
Reference VoltageAVDD
Output FormulaDAC_OUT = AVDD × (DIN / 1024)
Trigger ModesWrite trigger and timer trigger
Output Buffer EnableControlled by DACBE bit (0=disable, 1=enable)

Frequently asked questions

How do you enable the AX1003 DAC?

Set the DACEN bit to 1 in the ADCCFG2 register to enable the DAC.

What are the two trigger modes of the AX1003 DAC?

The DAC can operate in write‑trigger mode (DACTL=0) or timer‑trigger mode (DACTL=1), selected by the DACTL bit.

How is the DAC output voltage calculated?

The output voltage is calculated as DAC_OUT = AVDD × (DIN / 1024).

How can the DAC output buffer be enabled?

Set the DACBE bit to 1 in the ADCCFG2 register to enable the output buffer.

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