CD74AC02 is a quad 2-input NOR gate manufactured by Texas Instruments (TI). It utilizes Advanced CMOS Logic technology. The circuit has a typical propagation delay of 6ns (VCC = 5V, TA = 25oC, CL = 50pF), exceeds 2kV ESD protection (MIL-STD-883, Method 3015), SCR-Latchup-Resistant CMOS process and circuit design, speed of Bipolar FAST™/AS/S with significantly reduced power consumption, balanced propagation delays, AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage, ±24mA output drive current - fanout to 15 FAST™ ICs - drives 50Ω transmission lines.
About this manual
The CD54/74AC02 and CD54/74ACT02 are quad 2‑input NOR gates built with advanced CMOS logic technology. They feature a typical propagation delay of 6 ns at 5 V supply, 24 mA output drive current, and balanced propagation delays across all inputs. The devices operate from 1.5 V to 5.5 V (AC types) or 4.5 V to 5.5 V (ACT types) and provide up to 50 mA of source or sink current per output pin.
Ordering information includes three package options: 14‑lead CERDIP, PDIP, and SOIC, all rated for -55 °C to 125 °C. The datasheet lists absolute maximum ratings, thermal specifications, detailed DC electrical parameters, and switching characteristics such as input capacitance (10 pF) and propagation delay under various temperature and voltage conditions. Proper ESD handling is required.
What's inside
- Features
- Description
- Ordering Information
- Pinout
- Absolute Maximum Ratings
- Operating Conditions
- Thermal Information
- DC Electrical Specifications
- Switching Specifications
- Important Notice
Specifications
| Typical Propagation Delay | 6 ns |
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| Output Drive Current | 24 mA |
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| Supply Voltage Range (AC Types) | 1.5 V to 5.5 V |
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| Package Options | 14‑lead CERDIP, PDIP, SOIC |
Frequently asked questions
What is the typical propagation delay of the CD54/74AC02?
The typical propagation delay is 6 ns at a 5 V supply, 25 °C ambient temperature, and 50 pF load capacitance.
Which package types are available for these devices?
They are offered in 14‑lead CERDIP, PDIP, and SOIC packages.
How should the devices be handled to avoid electrostatic discharge damage?
They are sensitive to ESD, so users should follow proper IC handling procedures.