This document is a datasheet for the dsPIC30F2010 digital signal controller released by Microchip Technology Inc. in 2007. The datasheet provides detailed information on the high-performance features of the dsPIC30F2010 and the usage scenarios of the 16-bit digital signal controller.
The dsPIC30F2010 digital signal controller combines a 16‑bit RISC CPU with DSP features, offering a Harvard architecture, 30 MIPS processing speed and a wide range of on‑chip peripherals. It is targeted at motor‑control and power‑conversion applications.
Key features include 12 KB of flash program memory, 512 B of RAM, 1 KB EEPROM, three 16‑bit timers (configurable as 32‑bit), six PWM channels, a 10‑bit ADC with up to 1 Msps conversion rate, SPI, I²C, UART, and a quadrature encoder interface. The device operates from 2.5 V to 5.5 V and supports various power‑saving modes. This manual is written in Chinese.
| Flash program memory | 12 KB |
|---|---|
| RAM | 512 B |
| EEPROM | 1 KB |
| Maximum CPU performance | 30 MIPS |
| External clock input | 40 MHz |
| Oscillator with PLL | 4 MHz‑10 MHz with 4×, 8×, 16× PLL |
| Interrupt sources | 27 |
| Timer/Counter modules | 3 × 16‑bit (configurable as 32‑bit) |
| PWM output channels | 6 |
| ADC resolution | 10‑bit |
| ADC conversion rate | 1 Msps |
| ADC input channels | 6 |
It can operate up to 30 MIPS.
The device includes 12 KB of on‑chip flash program memory.
It contains 1 KB of non‑volatile EEPROM.
The controller offers six PWM output channels.