intersil Manuals

The ISL83387E is an Intersil-developed RS-232 transceiver that operates from 3.0V to 5.5V and meets EIA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. It also provides ±15kV ESD protection (IEC61000-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins). Target applications are PDAs, Palmtops, and notebook and laptop computers where low operational, and even lower standby power consumption is critical. Efficient on-chip charge pumps, coupled with manual and enhanced automatic powerdown functions, reduce the standby supply current to a 1µA trickle. TSSOP packaging, and the use of small, low value capacitors also ensure board space savings. Data rates greater than 250kbps are guaranteed at worst case load conditions. The ISL83387E features a VL pin that adjusts the logic pin output levels and input thresholds to values compatible with the VCC powering the external logic (e.g., a UART). This device includes an enhanced automatic powerdown function which powers down the on-chip power-supply and driver circuits. This occurs when all receiver and transmitter inputs detect no signal transitions for a period of 30 seconds. It power back up, automatically, whenever it senses a transition on any transmitter or receiver input. Table 1 summarizes the features of the ISL83387E, while A section provides more details.

This document introduces ICL3207 and ICL3217 two low power RS-232 transceivers, which meet EIA/TIA-232 and V.28/V.24 specifications, even at VCC=3.0V. This series of products are fully compatible with 3.3V, mixed 3.3V and 5.0V and 5.0V systems, and are a lower power, pin-for-pin replacement for '207 and '237 type devices.

Intersil ICL32X7E 3V to 5.5V powered RS-232 transmitters (five)/receivers (three) which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, they provide ±15kV ESD protection (IEC61000-4-2 Air Gap) and ±15kV Human Body Model protection on transmitter outputs and receiver inputs (RS-232 pins).

The ICL3237E is a family of 3.0V to 5.5V powered RS-232 transmitters/receivers that meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Additionally, it provides ±15kV ESD protection (IEC61000-4-2 Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-232 pins).

The ICL232 is a dual RS-232 transmitter/receiver interface circuit that meets all ElA RS-232C and V.28 specifications. It requires a single +5V power supply, and features two onboard charge pump voltage converters which generate +10V and -10V supplies from the 5V supply. The drivers feature true TTL/CMOS input compatibility, slew- rate-limited output, and 300Ω power-off source impedance. The receivers can handle up to +30V, and have a 3kΩ to 7kΩ input impedance. The receivers also have hysteresis to improve noise rejection.

This datasheet provides detailed information on Intersil X28C010/X28HT010 5V, Byte Alterable EEPROM

Intersil's X28C512, X28C513 are 64K x 8 EEPROMs fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. They feature the JEDEC approved pin out for byte wide memories, compatible with industry standard EPROMS. The X28C512, X28C513 support a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512, X28C513 also feature DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512, X28C513 support the software data protection option.

The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM that is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.

The X28HC64 is an 8K x 8 EEPROM fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable non-volatile memories, the X28HC64 is a 5V only device. It features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs. The X28HC64 supports a 64-byte page write operation, with an average write cycle of 2ms, and a complete memory rewrite time of 0.25 seconds. The chip has a durability of 1 million cycles and a data retention of 100 years.

This is the technical manual of HSP50110 Digital Quadrature Tuner. The tuner provides many of the functions required for digital demodulation, including carrier LO generation and mixing, baseband sampling, programmable bandwidth filtering, baseband AGC, and IF AGC error detection. Serial control inputs are provided which can be used to interface with external symbol and carrier tracking loops. These elements make the DQT ideal for demodulator applications with multiple operational modes or data rates. The DQT may be used with HSP50210 Digital Costas Loop to function as a demodulator for BPSK, QPSK, 8-PSK OQPSK, FSK, FM, and AM signals. The DQT processes a real or complex input digitized at rates up to 52 MSPS. The channel of interest is shifted to DC by a complex multiplication with the internal LO. The quadrature LO is generated by a numerically controlled oscillator (NCO) with a tuning resolution of 0.012Hz at a 52MHz sample rate. The output of the complex multiplier is gain corrected and fed into identical low pass FIR filters. Each filter is comprised of a decimating low pass filter followed by an optional compensation filter. The decimating low pass filter is a 3 stage Cascaded-Integrator-Comb (CIC) filter. The CIC filter can be configured as an integrate and dump filter or a third order CIC filter with a (sin(X)/X)3 response. Compensation filters are provided to flatten the (sin(X)/X)N response of the CIC. If none of the filtering options are desired, then the input is directly fed into the FIR filter.

This document introduces the Intersil HSP50210 Digital Costas Loop, which can be used to demodulate BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM waveforms.

The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It supports a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided. For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an on-board ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quarter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter. The serial interface for 3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface.

This document is the official datasheet for HSP43168 Dual FIR Filter. HSP43168 Dual FIR Filter is a low power fully static design with 8 sample input channels and two independent 8-bit FIR filters. It supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients.