National Monitor Manuals

The DS90CF363 is a 3.3V LVDS transmitter, 18-bit Flat Panel Display (FPD) link - 65 MHz. It converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF383B is a programmable LVDS transmitter that converts 28 bits of CMOS/TTL data into four LVDS data streams. It supports a transmit clock frequency of 65 MHz and can transmit 24 bits of RGB data and 3 bits of LCD timing and control data at a rate of 455 Mbps per LVDS data channel. The DS90CF383B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

DS90CF386/DS90CF366 is a LVDS receiver chip produced by TI company. It can convert four LVDS data streams (up to 2.38 Gbps throughput or 297.5 megabytes/second bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL)

The DS90CF383 is a +3.3V LVDS transmitter from National Semiconductor Corporation that supports a 24-bit Flat Panel Display (FPD) Link, and uses a 65 MHz transmit clock to sample 28 bits of input data per cycle and transmit it at a rate of 455 Mbps per LVDS data channel.