Update: 28 September, 2023
The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control.
File format: PDF
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MD5 Checksum: 09F350F24B645F61BA237FBCA439E2D1
Publication date: 01 August, 2012
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PDF Link: TEXAS INSTRUMENTS CDCF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER handbook PDF