Update: 30 September, 2023
The CDC2516 3.3-V Phase-Lock Loop Clock Driver is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2516 does not require external RC network.
File format: PDF
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MD5 Checksum: 976B3B35BD957B3CE604187D3E3065DD
Publication date: 01 August, 2012
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PDF Link: TEXAS INSTRUMENTS CDC2516 handbook PDF