National Semiconductor 100331 Low Power Triple D Flip-Flop handbook

Update: 01 October, 2023

The 100331 is a low power triple D flip-flop with true and complement outputs, a Common Clock (CPC) and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kΩ pull-down resistors.

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File format: PDF

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MD5 Checksum: B18A219DEB24E2976EBB6119A7FB7E36

Publication date: 01 June, 2012

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PDF Link: National Semiconductor 100331 Low Power Triple D Flip-Flop handbook PDF