intersil X28HC256 Manual

Update: 30 September, 2023

The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM that is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.

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Brand: intersil

File format: PDF

Size: 312 KB

MD5 Checksum: 4C88F28E3760664C60AE356925D8E05D

Publication date: 28 March, 2012

Downloads: -

PDF Link: intersil X28HC256 Manual PDF