Hitachi manuals, page 12
HITACHI HD74ALVCH16827 handbook
HD74ALVCH16827 is a 20-bit buffer/driver with 3-state outputs. It is composed of two 10-bit sections with separated output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is high, the outputs of that 10-bit buffer section are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
HITACHI HM62256B Series handbook
The HM62256B series is a 32,768 word × 8 bit high speed CMOS static RAM that utilizes 0.8 µm Hi-CMOS process technology to achieve higher performance and lower power consumption. The device is available in 8 × 14 mm TSOP, 8 × 13.4 mm TSOP with a thickness of 1.2 mm, 450 mil SOP (footprint pitch width), 600 mil plastic DIP, or 300 mil plastic DIP packages for high density mounting. It offers low power standby power dissipation and is therefore suitable for battery back-up systems.
HITACHI HD155101BF RF Single-chip Linear IC for GSM EGSM Systems
The HD155101BF is an RF single-chip linear IC developed for GSM and EGSM cellular systems. It integrates most of the functions of a transceiver, including the bias circuit for an RF LNA, a 1st mixer, 1st-IF amplifier, 2nd mixer, AGC amplifier, IQ quadrature demodulator for the receiver, and an IQ quadrature modulator and offset PLL for the transmitter. It also includes on-chip dividers for the 1st and 2nd local oscillator signals and a 90° phase splitter, as well as control circuits for power saving modes. The HD155101BF can operate down to 2.7V and is housed in a 48-pin LQFP SMD package. By adding a PLL frequency synthesizer IC, a power amplifier, and some external components, the HD155101BF can be used to create a small-sized transceiver handset for GSM and EGSM. The HD155101BF is fabricated using a 0.6µm double-polysilicon Bi-CMOS process.
HITACHI HD74BC244A handbook
The HD74BC244A is an octal buffer/line driver with three-state outputs. It utilizes Bi-CMOS process to provide high drivability and operation equal to or better than high speed bipolar standard logic ICs. The device features low power dissipation, approximately 1/5 of high speed bipolar logic ICs at a frequency of 10 MHz. It has a 20-pin package and is a non-inverting buffer with two active low enables (1G and 2G), each controlling 4 buffers independently.
HITACHI HD74ALVCHS162830 1-bit to 2-bit Address Driver with 3-state Outputs
The HD74ALVCHS162830 is a 1-bit to 2-bit address driver designed for 2.3 V to 3.6 V VCC operation. The driver has a high output current of ±12 mA (@VCC=3.0 V) and can eliminate the need for external pull-up/pull-down resistors on the data inputs. The driver also has diodes to clamp overshoot.
HITACHI HD6350/HD6850 SERIES DATA SHEET
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HITACHI H8S/2345 H8S/2344 H8S/2343 H8S/2341 H8S/2340 solutions manual
This manual describes the hardware features of the H8S/2345 F-ZTATTM series chips, suitable for H8S/2345, H8S/2344, H8S/2343, H8S/2341, H8S/2340 chips
HITACHI HD404358 Series
The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input capture timer, and two low-power dissipation modes. The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the HD407A4359 with 16-kword PROM. The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum instruction cycle time: 0.47 µs) The HD407A4359 is a PROM version (ZTAT microcomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTAT version is 27256-compatible.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
HITACHI HM5118165 Series 16 M EDO DRAM (1-Mword × 16-bit) 1 k Refresh
The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin plastic TSOP II.
HITACHI HZ-L Series handbook
This document describes the HZ-L series silicon epitaxial planar zener diode for low noise applications. It has a diode noise level approximately 1/3-1/10 lower than the HZ series, making it ideal for stabilized power supplies and other applications. It features low leakage, low zener impedance, and a maximum power dissipation of 400mW. The zener voltage ranges from 5.2V to 38V, providing flexibility for various applications.
Hitachi Universal Storage Platform V/VM Universal Volume Manager User Guide
Describes the features and characteristics of Hitachi Universal Storage Platform V/VM Universal Volume Manager
Hitachi VSP Hitachi Volume Shredder User Guide
This guide describes the features and usage of Hitachi Volume Shredder.
Hitachi Dynamic Link Manager Software User's Guide
This document is the user's guide for Hitachi Dynamic Link Manager software, which describes the features and characteristics of the software.
HITACHI CUSTOMER S ACCEPTANCE SPECIFICATIONS SP14Q002-C2A CONTENTS
This is a customer acceptance specification which mainly introduces the product's overall specifications, absolute maximum ratings, electrical characteristics, optical characteristics, block diagram, interface timing, outline dimensions, quality standards, design precautions, lot mark, use precautions and digitizer technical specifications.
HITACHI Projector PJ-TX100 User's Manual - Operating Guide
This user manual is the operating guide for the Projector PJ-TX100, including safety precautions and operating instructions.