MOTOROLA Manuals

This document is about MPC5200 hardware specifications, mainly introduces the features of MPC5200, including processor core, memory controller, external bus interface and so on.

MPC2605 is a single chip, 256KB integrated look-aside cache with copy-back capability designed for PowerPC applications (MPC603 and MPC604). Using 0.38µm technology along with standard cell logic technology, the MPC2605 integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2 cache with one, two, or four chips on a 64-bit PowerPC bus.

The MPC2105C and MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.

This is the MPC2105A/B and MPC2106A/B Fast SRAM 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms.

MOTOROLA FAST SRAM is a 256KB/512KB BurstRAM secondary cache module specifically designed for the PowerPC 60x microprocessor family in compliance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.

The MPC2104/5/6/7 are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchronous data RAMs. The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18; the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the 5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst capability is provided in that two burst addresses bypass the addr

MPC2002 and MPC2003 are Motorola's 256KB and 512KB BurstRAM secondary cache modules for PowerPC systems. The modules are configured as 32K x 72 and 64K x 72 bits in a 136-pin dual read single inline memory module (DIMM). The module uses four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0-PD2 are reserved for density and speed identification.

The MPC2001 is a 256KB asynchronous secondary cache module from Motorola that is designed for PowerPC 60x processors. The module is configured as 32K x 64 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses eight of Motorola's MCM6206 CMOS RAMs. Eight write enables are provided for byte write control. The cache is designed to interface with the PowerPC 60x bus and requires external tag. PD0 – PD2 are reserved for density and speed identification. The cache is plug and pin compatible with Motorola's MPC2002 and MPC2003 BurstRAM synchronous cache modules.

This document is the user manual for the MPC180LMB Security Processor, providing information on the features and characteristics of the product.

The MPC180 is a security processor with flexible and powerful features, suitable for various networking systems. It can off-load computationally intensive security functions such as key generation and exchange, authentication, and bulk data encryption. The MPC180 is optimized to process all of the algorithms associated with IPSec, IKE, WTLS/WAP, and SSL/TLS.

This document introduces a quad H-bridge micromotor driver named MPC17550, which features a DC/DC boost converter and independent control. It is suitable for portable electronic devices powered by two to four cell NiCd/NiMH batteries and can drive tiny bipolar stepper motors and/or brush DC motors. It has a low current-drain standby mode and PWM control capability.

The 17529 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar step motors and/or brush DC-motors (e.g., cameras and disk drive head positioners).

This document from MOTOROLA Semiconductor provides information on a new product, the 17517 dual motor driver IC, which is designed for controlling small DC motors and solenoids in portable electronic applications. The IC can operate efficiently with low voltage and is easily interfaced with low-cost MCUs via parallel logic. It supports two-motor operation or motor plus solenoid operation with synchronous rectification.

The 17510 is a monolithic H-Bridge designed to be used in portable electronic applications such as digital and SLR cameras to control small DC motors.