MOTOROLA Manuals

The MC10/100EL57 is a 4:1 multiplexer from Motorola. It can be used in 4:1 mode or 2:1 mode by switching the SEL1 line. In 4:1 mode, SEL0 selects between D0 and D1. In 2:1 mode, SEL0 selects between D0 and D1. The EL57 has a fully differential architecture, making it ideal for use in low skew applications such as clock distribution.

The MC10/100EL57 is a fully differential 4:1 multiplexer from Motorola. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EL57 makes it ideal for use in low skew applications such as clock distribution. The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).

The document is about MC100LVEL17 product technical data manual. MC100LVEL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a –3.3V or +3.3V supply voltage. MC100EL17 is pin and functionally equivalent to the MC100LVEL17, but is specified for operation at the standard 100E ECL voltage supply. The LVEL17 provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for the LVEL17 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

The MC100LVEL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a –3.3V or +3.3V supply voltage. The MC100EL17 is pin and functionally equivalent to the MC100LVEL17, but is specified for operation at the standard 100E ECL voltage supply. The LVEL17 provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for the LVEL17 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

The MC100LVEL29 is a dual master-slave flip flop.

The MC100LVEL29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but is specified for operation at the standard 100E ECL voltage supply. A VBB output is provided for AC coupling, refer to the interfacing section of the ECLinPS Data Book (DL140) for more information on AC coupling ECL signals. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the D input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up. Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.

The MC100LVEL30 is a triple master-slave D flip-flop with differential outputs. The MC100EL30 is pin and functionally equivalent to the MC100LVEL30 but is specified for operation at the standard 100E ECL voltage supply. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input, individual Reset inputs are provided for each flip-flop. Both the Set and Reset inputs function asynchronously and overriding with respect to the clock inputs.

The MC100LVEL30 is a triple master-slave D flip flop with differential outputs. The MC100EL30 is pin and functionally equivalent to the MC100LVEL30 but is specified for operation at the standard 100E ECL voltage supply. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronously and overriding with respect to the clock inputs.

The MC10EL/100EL31 is a D flip-flop with set and reset. It has high performance capabilities and is ideally suited for those applications which require the ultimate in AC performance.

MC10EL/100EL32 is an integrated ÷2 divider, which has features such as 510ps Propagation Delay, 3.0GHz Toggle Frequency, High Bandwidth Output Transitions, 75kΩ Internal Input Pulldown Resistors, >1000V ESD Protection.

10EL32 is a MC10EL/100EL32 series product, an integrated 1/2 divider, with 510ps propagation delay, 3.0GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors, >1000V ESD protection

The MC10EL/100EL33 is an integrated ÷4 divider. It features a propagation delay of 650ps, a toggle frequency of 4.0GHz, and high bandwidth output transitions. The device also has 75kΩ internal input pulldown resistors and >1000V ESD protection.

The MC10EL/100EL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the E404 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E404, the EL05 is ideally suited for those applications which require the ultimate in AC performance. Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the EL05 to also be used as a 2-input differential OR/NOR gate. The differential inputs employ clamp circuitry so that under open input conditions (pulled down to VEE) the input to the AND gate will be HIGH. In this way, if one set of inputs is open, the gate will remain active to the other input.

This datasheet provides the technical specifications of the MC10EL/100EL05.