MOTOROLA Manuals

The MC100LVEL29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but is specified for operation at the standard 100E ECL voltage supply. A VBB output is provided for AC coupling, refer to the interfacing section of the ECLinPS Data Book (DL140) for more information on AC coupling ECL signals. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the D input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up. Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.

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The MC100LVEL29 is a dual master-slave flip flop.

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The MC100LVEL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a –3.3V or +3.3V supply voltage. The MC100EL17 is pin and functionally equivalent to the MC100LVEL17, but is specified for operation at the standard 100E ECL voltage supply. The LVEL17 provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for the LVEL17 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

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The document is about MC100LVEL17 product technical data manual. MC100LVEL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a –3.3V or +3.3V supply voltage. MC100EL17 is pin and functionally equivalent to the MC100LVEL17, but is specified for operation at the standard 100E ECL voltage supply. The LVEL17 provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for the LVEL17 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01µf capacitor. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability.

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The MC10/100EL57 is a fully differential 4:1 multiplexer from Motorola. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EL57 makes it ideal for use in low skew applications such as clock distribution. The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).

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The MC10/100EL57 is a 4:1 multiplexer from Motorola. It can be used in 4:1 mode or 2:1 mode by switching the SEL1 line. In 4:1 mode, SEL0 selects between D0 and D1. In 2:1 mode, SEL0 selects between D0 and D1. The EL57 has a fully differential architecture, making it ideal for use in low skew applications such as clock distribution.

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The MC10/100EL57 is a fully differential 4:1 multiplexer. The device can also be used as a differential 2:1 multiplexer. It has multiple VBB outputs for single-ended or AC coupled interfaces.

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The MC10EL/100EL52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the E452 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452 the EL52 is ideally suited for those applications which require the ultimate in AC performance. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EL52 allow the device to also be used as a negative edge triggered device. The EL52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable.

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The MC10EL/100EL52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the E452 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452, the EL52 is ideally suited for those applications which require the ultimate in AC performance. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EL52 allow the device to also be used as a negative edge triggered device. The EL52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable.

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The EL51 is a differential clock D flip-flop with reset. The device is functionally similar to the E151 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E151 the EL51 is ideally suited for those applications which require the ultimate in AC performance. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input (pulled down to VEE) conditions.

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MC10EL/100EL51 is a differential clock D flip-flop with reset

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MC10EL/100EL35 is a high-speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. It features a 525ps propagation delay, 2.2GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors, and >1000V ESD protection.

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The MC10EL/100EL35 is a high speed JK flip-flop with 525ps propagation delay, 2.2GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors and >1000V ESD protection.

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The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications.

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The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications

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The MC10EL/100EL33 is a 1:4 divider in the MC10EL/100EL series. It features 650ps propagation delay, 4.0GHz toggle frequency, high bandwidth output transitions, 75kΩ internal input pulldown resistors, and >1000V ESD protection.

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The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT22 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.

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This document is about the technical data of MC10ELT/100ELT21

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