The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for
The NXP 74AUP1G74 is a low-power, low-voltage single positive-edge triggered D-type flip-flop featuring individual data (D), clock (CP), set (SD), and reset (RD) inputs. It includes complementary Q and Q outputs, with the SD and RD acting as asynchronous active LOW inputs that operate independently of the clock.
The device utilizes Schmitt trigger action at all inputs to ensure tolerance against slower input rise and fall times across its entire supply voltage range of 0.8 V to 3.6 V. It offers multiple package options, including VSSOP8 and various XSON8 configurations, and is specified for operation from -40 °C to +125 °C.
| Supply voltage range | 0.8 V to 3.6 V |
|---|---|
| Operating temperature range | -40 °C to +125 °C |
| Maximum static supply current (Icc) | 0.9 mA |
| ESD protection HBM | > 5000 V |
| Package types | VSSOP8, XSON8 (multiple variants) |
The SD and RD are asynchronous active LOW inputs that operate independently of the clock input.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse.
The device operates with a supply voltage ranging from 0.8 V to 3.6 V.