NXP 74AUP1G74 flip-flop

Update: 25 September, 2023

The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for

---

Brand: NXP

File format: PDF

Size: 345 KB

MD5 Checksum: B86BA45682FF1D14215E9038BCB77720

Publication date: 12 May, 2014

Downloads: -

PDF Link: NXP 74AUP1G74 flip-flop PDF