Update: 28 September, 2023
The document describes the features and characteristics of the 74V1G77 model product. The product is an advanced high-speed CMOS single D-type latch fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is designed to operate from 2V to 5.5V, making it ideal for portable applications. The latch is controlled by a latch enable input (LE), and the Q output precisely follows the data input when the LE input is high. When the LE input is low, the Q output is latched to the logic level of the D input data. The product provides power down protection on inputs and can accept voltages from 0 to 7V on inputs without regard to the supply voltage. It can be used to interface between 5V and 3V. The product is equipped with protection circuits against static discharge, providing ESD immunity and transient excess voltage protection.
File format: PDF
Size: -
MD5 Checksum: 58AFC4C4CA93F94E3553357723DE38B3
Publication date: 10 August, 2012
Downloads: -
PDF Link: ST 74V1G77 SINGLE D-TYPE LATCH handbook PDF