Update: 28 September, 2023
The document describes the features and characteristics of the 74LVC125A low voltage CMOS quad bus buffer. It is suitable for voltage operations from 1.65 to 3.6V and is ideal for low power and low noise applications. It can be interfaced with a 5V signal environment for inputs in mixed 3.3/5V systems. The device requires the same 3-STATE control input G to be set high in order to put the output into a high impedance state. It has higher speed performance at 3.3V compared to the 5V AC/ACT family, while consuming lower power. All inputs and outputs are equipped with protection circuits against static discharge, providing them with 2KV ESD immunity and transient excess voltage.
File format: PDF
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MD5 Checksum: 41D6D67B3522A741212A0DC57C407797
Publication date: 10 August, 2012
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PDF Link: ST 74LVC125A handbook PDF