ST 74VHC573 handbook

Update: 28 September, 2023

The document describes an advanced high-speed CMOS octal D-type latch with three-state outputs and non-inverting function. The product is fabricated using sub-micron silicon gate and double-layer metal wiring C2MOS technology, and it features high noise immunity, low power dissipation, and low noise. It has power down protection on inputs and is compatible with 5V to 3V interfaces. All inputs and outputs are equipped with protection circuits against static discharge, providing 2KV ESD immunity and transient excess voltage protection.

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File format: PDF

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MD5 Checksum: 3FFCD286D533557108EDBFB1A5677FAE

Publication date: 10 August, 2012

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PDF Link: ST 74VHC573 handbook PDF