Update: 30 September, 2023
This document introduces the features of 256Kbit and 128Kbit Serial I²C Bus EEPROM With Three Chip Enable Lines, including compatible with I2C Extended Addressing, Two Wire I2C Serial Interface Supports 400 kHz Protocol, Single Supply Voltage, Hardware Write Control, BYTE and PAGE WRITE, RANDOM and SEQUENTIAL READ Modes, Self-Timed Programming Cycle, Automatic Address Incrementing, Enhanced ESD/Latch-Up Behavior, More than 100,000 Erase/Write Cycles, More than 40 Year Data Retention
File format: PDF
Size: -
MD5 Checksum: CFB361026D48979B1FB2673812C8C9DD
Publication date: 09 August, 2012
Downloads: -
PDF Link: ST M24256-B M24128-B 256Kbit 128Kbit Serial I C Bus EEPROM With Three Chip Enable Lines handbook PDF