ST 74V1T79 handbook

Update: 28 September, 2023

The document describes a high-speed CMOS single positive edge triggered D-type flip-flop. The flip-flop is fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology and is designed to operate from 4.5V to 5.5V. It features high speed, low power dissipation, compatibility with TTL outputs, and can be used to interface 5V to 3V systems.

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File format: PDF

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MD5 Checksum: 2BDDAF5A3F20E85857411377FC8A837D

Publication date: 08 August, 2012

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PDF Link: ST 74V1T79 handbook PDF