TEXAS INSTRUMENTS CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER LVPECL I/O + ADDITIONAL LVCMOS OUTPUT handbook

Update: 30 September, 2023

The CDCM1802 is a clock buffer with a programmable divider, LVPECL I/O and additional LVCMOS output. It distributes one differential clock input to one LVPECL differential clock output and one LVCMOS single-ended output. The programmable output divider is suitable for LVPECL and LVCMOS outputs. The 1.6-ns output skew between LVCMOS and LVPECL transitions minimizes noise. The device operates at a supply voltage of 3.3 V (2.5 V functional) and has a signaling rate of up to 800 MHz LVPECL and 200 MHz LVCMOS. The differential input stage has a wide common-mode range and also provides a VBB bias voltage output for single-ended input signals. The receiver input threshold is ±75 mV. The device is packaged in a 16-pin QFN package (3 mm x 3 mm).

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Publication date: 01 August, 2012

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PDF Link: TEXAS INSTRUMENTS CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER LVPECL I/O + ADDITIONAL LVCMOS OUTPUT handbook PDF