Update: 30 September, 2023
The CDC509 is a high-performance, low-jitter, low-skew phase-lock loop (PLL) clock driver from Cypress Semiconductor. It uses a PLL to precisely align the feedback (FBOUT) output to the clock (CLK) input signal, both in frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3 V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC509 does not require external RC networks. The PLL's loop filter is integrated on-chip, reducing PCB area.
File format: PDF
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MD5 Checksum: 92249B9F9AF64C0B17F0B57C267D7E8E
Publication date: 01 August, 2012
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PDF Link: TEXAS INSTRUMENTS CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER handbook PDF