Update: 01 October, 2023
CDC2510C is a 3.3V low-skew, low-jitter, phase-lock loop (PLL) clock driver released by TI. It uses a PLL to precisely align the feedback output (FBOUT) with the clock input (CLK) signal in both frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V. It also provides integrated series damping resistors, making it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled through a single output enable input. When the G input is high, all outputs are enabled.
File format: PDF
Size: -
MD5 Checksum: A568C79DC39BCF5E29A775A021A4E9F3
Publication date: 01 August, 2012
Downloads: -
PDF Link: TEXAS INSTRUMENTS CDC2510C handbook PDF