Update: 29 September, 2023
The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50-Ω transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external RC network.
File format: PDF
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MD5 Checksum: 7CF8E494F6F15C74D256DBF5F474CF17
Publication date: 01 August, 2012
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PDF Link: TEXAS INSTRUMENTS CDC2536 handbook PDF