MOTOROLA Semiconductor MC10E150/MC100E150 handbook(1)

Update: 30 September, 2023

The MC10E/100E150 is a 6-bit D latch with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.

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MD5 Checksum: 42ECF342AEF4145A0613CECAC11D5408

Publication date: 09 July, 2012

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PDF Link: MOTOROLA Semiconductor MC10E150/MC100E150 handbook(1) PDF