YAMAHA XCR3128A: 128 Macrocell CPLD with Enhanced Clocking

Update: 30 September, 2023

This application note introduces the features and characteristics of Xilinx's XPLA™ PLD. This PLD uses Fast Zero Power design technology, which provides ultra-low power and very high speed. This PLD supports 3V voltage and can be programmed in-system using a JTAG interface. This PLD also has a 4-pin JTAG interface and high-performance pin-to-pin delays.

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File format: PDF

Size: -

MD5 Checksum: 31C3537D248F7FC91D21F759DD28C5D4

Publication date: 12 June, 2012

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PDF Link: YAMAHA XCR3128A: 128 Macrocell CPLD with Enhanced Clocking PDF