Update: 30 September, 2023
5476 is a dual master-slave J-K flip-flop with complementary outputs produced by National Semiconductor. It has two independent positive pulse triggers, which process J and K data after a complete clock pulse. When the clock is low, the slave is isolated from the master. When the clock is positive, the data from the J and K inputs is transferred to the master. When the clock is high, the J and K inputs are disabled. When the clock is negative, the data from the master is transferred to the slave. The logic state of J and K inputs must not be allowed to change while the clock is high. The data is transferred to the outputs on the falling edge of the clock pulse. When setting or resetting the outputs, a low logic level on the preset or clear inputs will be independent of the logic levels of the other inputs.
File format: PDF
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MD5 Checksum: 4E9E36CD93E71607F56380F0B6C739A9
Publication date: 12 June, 2012
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PDF Link: National Semiconductor 5476/DM5476/DM7476 handbook PDF