TEMIC TS80C31X2 handbook

Update: 29 September, 2023

TEMIC TS80C31X2 is a high-performance CMOS and ROMless version of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TEMIC TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscillator, and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART), and an X2 speed improvement mechanism. The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C31X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode, the CPU is frozen while the timers, the serial port, and the interrupt system are still operating. In the power-down mode, the RAM is saved and all other functions are inoperative.

---

Brand: TEMIC

File format: PDF

Size: 288 KB

MD5 Checksum: 6CB91ECC15DDA30B8DEF84B98F9C6663

Publication date: 11 June, 2012

Downloads: -

PDF Link: TEMIC TS80C31X2 handbook PDF