MOTOROLA MCM67M518 Data Sheet

Update: 29 September, 2023

The MCM67M518 is a synchronous static random access memory designed to provide a burstable, high-performance, secondary cache for the MC68040 and PowerPC microprocessors. It is fabricated using Motorola's high-performance silicon-gate BiCMOS technology and integrates input registers, a 2-bit counter, high-speed SRAM, and high drive capability outputs onto a single monolithic circuit. The synchronous design allows precise cycle control with the use of an external clock. Bursts can be initiated with either transfer start processor or transfer start cache controller input pins. Write cycles are internally self-timed and initiated by the rising edge of the clock input.

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Brand: MOTOROLA

File format: PDF

Size: 209 KB

MD5 Checksum: 71029F97DDE44F882D55C824C1E808F7

Publication date: 05 June, 2012

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PDF Link: MOTOROLA MCM67M518 Data Sheet PDF