MOTOROLA MCM64PC32 MCM64PC64 DATA SHEET
The MCM64PC32 (256K) and MCM64PC64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PC32 is configured as 32K x 64 bits and the MCM64PC64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0-PD3 map into the Triton II chip set for auto-configuration of the cache control. Pentium-Style Burst Counter on Chip. Pipelined Data Out. 160 Pin Card Edge Module. Address Pipeline Supported by ADSP Disabled with Ex. All Cache Data and Tag I/Os are TTL Compatible. Three State Outputs. Byte Write Capability. Fast Module Clock Rate: 66 MHz. Fast SRAM Access Times: 15 ns for Tag RAM, 8 ns for Data RAMs. One-Cycle Deselect Data RAMs. Decoupling Capacitors for Each Fast Static RAM. High Quality Multi-Layer FR4 PWB with Separate Power and Ground.
Brand: MOTOROLA
File format: PDF
Size: 181 KB
MD5 Checksum: 761C8F14F286D9C5D18BA012E97CE1C9
Publication date: 04 June, 2012
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PDF Link: MOTOROLA MCM64PC32 MCM64PC64 DATA SHEET PDF