Update: 30 September, 2023
The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver from Texas Instruments. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at 3.3V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input. When the G input is high, the outputs switch in phase.
File format: PDF
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MD5 Checksum: D4A5F694EB5D51275AA03D06A283D8F3
Publication date: 10 May, 2012
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PDF Link: TEXAS INSTRUMENTS CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER handbook PDF