Update: 30 September, 2023
This document introduces the LTC3831, a high power, high efficiency DDR memory termination switching regulator controller. The device uses a synchronous switching architecture with N-channel MOSFETs, and the output voltage is equal to 1/2 of the external supply or reference voltage. The LTC3831 can sense output current and regulate it through the drain-source resistance of the upper N-channel MOSFET, thereby providing adjustable current limit without a current sense resistor. The device can operate with a supply voltage as low as 3V and with a maximum duty cycle of >91%. It includes a fixed frequency PWM oscillator for low output ripple operation.
File format: PDF
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MD5 Checksum: 500B2B406E6072C9F894648D91603A2E
Publication date: 09 May, 2012
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PDF Link: LINEAR TECHNOLOGY LTC3831 Manual PDF