Update: 29 September, 2023
The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se- ries Stub Termination Logic) for active termination of DDR- SDRAM. The device utilizes an internal operational amplifier to provide linear regulation of VTT without the need for expensive external components. The output stage prevents shoot through while delivering 1.5A continuous current and maintaining excellent load regulation. The LP2994 also in- corporates an active low shutdown pin to tri-state the output during Suspend To Ram (STR) states. Patents Pending Features: Source and sink current, Low external component count, Independent analog and power rails, Linear topology, Small package SO-8, Low cost and easy to use, Shutdown pin. Applications: SSTL-2, SSTL-3, DDR-SDRAM Termination, DDR-II Termination.
File format: PDF
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MD5 Checksum: 724B21CE96D480BB4BF968B19622C0CF
Publication date: 08 May, 2012
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PDF Link: National Semiconductor LP2994 DDR Termination Regulator handbook PDF