Update: 01 October, 2023
MAX9324 is a low-skew, low-jitter, clock and data driver that distributes a differential LVPECL input to four differential LVPECL outputs and one single-ended LVCMOS output. When the differential inputs are equal to GND or are left open, all outputs default to logic low. The MAX9324 operates from 3.0V to 3.6V, making it ideal for 3.3V systems, and consumes only 25mA (max) of supply current. The MAX9324 features low 150ps (max) part-to-part skew, low 15ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. CLK_EN and SEOUT_Z control the status of the various outputs. Asserting CLK_EN low configures the differential (Q_, Q_) outputs to a differential low condition and SEOUT to a single-ended logic-low state. CLK_EN operation is synchronous with the CLK_ inputs. A logic high on SEOUT_Z places SEOUT in a high-impedance state. SEOUT_Z is asynchronous with the CLK (CLK) inputs. The MAX9324 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm × 4mm thin QFN packages and operates over the extended (-40°C to +85°C) temperature range. Applications Precision Clock Distribution Low-Jitter Data Repeater Data and Clock Driver and Buffer Central-Office Backplane Clock Distribution DSLAM Backplane Base Station ATE Features o 15ps Differential Output-to-Output Skew o 1.7psRMS Added Random Jitter o 150ps (max) Part-to-Part Skew o 450ps Propagation Delay o Synchronous Output Enable/Disable
File format: PDF
Size: -
MD5 Checksum: A07FE4D2E94651743A72576AB8E77E19
Publication date: 08 May, 2012
Downloads: -
PDF Link: MAXIM MAX9324 Manual PDF