Update: 30 September, 2023
CDC5801 is a low jitter clock multiplier and divider with programmable delay and phase alignment. It features a single-ended input and a differential output, supporting LVPECL, LVDS and LVTTL signal levels. CDC5801 operates in the frequency range of 19 MHz to 125 MHz, with an output frequency range of 150 MHz to 500 MHz. It has a 2.6 mUI programmable bidirectional delay step, with a typical phase jitter of 8.0-ps (12 kHz to 20 MHz) @ 500 MHz and a typical RMS period jitter of 2.1-ps (entire frequency band) @ 500 MHz. CDC5801 supports three power operating modes to minimize power consumption. It has a typical power consumption of 200 mW@500 MHz. CDC5801 is packaged in a Shrink Small-Outline Package (DBQ), with no external components required for PLL. It also has a Spread Spectrum Clock Tracking ability to reduce EMI. CDC5801 is suitable for use in video graphics, gaming products, data communications and telecommunications.
File format: PDF
Size: -
MD5 Checksum: 8E41BCBF398A0822C0F256E874E22DDC
Publication date: 05 May, 2012
Downloads: -